Mohsen Ahmadvand
Telephone: +98(81)38411426
Email: ahmadvand@hut.ac.ir
Address: Shahid Fahmideh.St,Hamedan,IRAN
Research Interests 
  • Computer Arithmetic
  • Hardware-Software Codesign
  • Image Coding
  • VHDL
Publications

  • Yarallah Koolivand, Yasser Rezaeiyan, Omid Shoaei, Shahin JafarabadiAshtiani, Ali Moftakharzadeh & Mohsen Ahmadvand : "Modified linear in dB, sub 0.2 dB gain-step CMOS programmable gain amplifier for ultrasound applications" accepted in Analog Integrated Circuits and Signal Processing , Springer 2019, ISSN 0925-1030 Volume 99 Number 3, 99:497–508, April 2019

  • M.Ahmadvand, A. Ezhdehakosh: "A New Pipelined Architecture for JPEG2000 MQ-Coder” accepted in World Congress on Engineering and Computer Science (WCECS 2012), USA, August 2012

  • M.Ahmadvand, A. Ezhdehakosh: "GPU-Based Implementation of JPEG2000 Encoder” accepted in 18th International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA'12), USA, July 2012

  • H.Parandeh-Afshar, M.Ahmadvand, S.M. Fakhraie: "A Novel Merged Multiplier-Accumulator Embedded in DSP Coprocessor,” accepted in 13th IEEE International Conference on Electronics, Circuits and Systems, ICECS, NICE, France, December 2006

  • A.Aminlou, M.Homayouni, M.Ahmadvand, “Pipelined Architectures of MQ-Coder: Verification Approach”, accepted in 3rd IEEE International Conference on Circuits and Systems for Communications, (ICCSC 2006), Politehnica University, Bucharest, Romania, July 2006

  • M.Ahmadvand, A.Aminlou, “Deterministic Verification for Pipelined Architectures of JPEG2000 MQ-Coder”, RISP International Workshop on Nonlinear Circuit and Signal Processing (NCSP'05), Hawaii, March 2005

  • H.Parandeh-Afshar, M.Ahmadvand, C.Lucas: "Improving routing in configurable devices by hardware Implementation of simulated annealing algorithm," in Proceeding of International CSI Computer Conference (CSICC 2004), Tehran, Iran, February 2004

  • M. Ahmadvand, O. Fatemi, H.Badakhshannoory, M.R. Hashemi, “A Novel Pipelined Architecture for JPEG2000 MQ-Coder with Reduced Hardware Resource Requirement”, 24th Picture Coding Symposium, San Francisco, CA, USA, May 2004

  • M. Ahmadvand, A. Shahrokhi, O. Fatemi, “A High-Speed Pipelined Architecture for MQ-Coder of JPEG2000 Standard” The 22nd Biennial Symposium on Communications, Ontario-Canada, June 2004

Courses Taught

  • Digital Logic Circuits

  • Computer Architecture

  • Digital Electronics

  • Data Communication

  • Computer Aided Digital System Design

  • Electrical Circuits 1 

 

Academic Experiences

  • Design a Telecommunication System Switch (Private Branch Exchange System) by using ARM-9 processor, Xilinx FPGA, DSP, HDLC Controller, SLIC and CODEC, December 2010 - September 2013

  • Design a Medical Image Compressor by VHDL, May 2004 - July 2006

  • Design, Implementation and Synthesis a High Through-put Binary Arithmetic Coder (MQ-Coder) by VHDL on VIRTEX FPGA, September 2002 - June 2004

  • Design and Implementation an Array Multiplier Unit by VHDL, February 2004

  • Design and Implementation a SRT Radix-2 Divider by VHDL, February 2003

  • Implementation a Fault Simulator for Verilog by C++, November 2002

  • Design and Implementation a Pipelined DLX Processor by VHDL, August 2001

Honors and Awards

  • Best Lecturer at the Computer Engineering Department, Hamedan University of Technology, May 2018, May 2014, May 2012

  • Ranked 8th among 8,000 participants in the nationwide university entrance exam for M.Sc. degree of computer engineering, September 2002